Low-Power Edge Computing 

Edge computing has gained public attention on various industries by enabling real-time data processing and analysis at the edge.

However, it remains challenging to provide low-power computing solutions that are capable of performing complex computational tasks in a resource-constrained environment. To address this challenge, our group are exploring across various levels, including device, circuit, architecture and algorithm, for many applications, including video understanding, natural language understanding, hand-held ultrasound devices, hearables, and more.

Research Team

Related Recent Publications

• Lee K., A. P. Chandrakasan, “Understanding the Energy vs. Adversarial Robustness Trade-Off in Deep Neural Networks,” IEEE Workshop on Signal Processing Systems (SiPS), Oct. 2021. [link]
• Brahma K., V. Kumar, A. E. Samir, A. P. Chandrakasan, Y. C. Eldar, “Efficient Binary CNN for Medical Image Segmentation”, IEEE International Symposium on Biomedical Imaging (ISBI), Apr. 2021. [link]
• Ji Z., W. Jung, J. Woo, K. Sethi, S. Lu, A. P. Chandrakasan, “CompAcc: Efficient Hardware Realization for Processing Compressed Neural Networks Using Accumulator Arrays,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2020. [link]
• Wang M., A. P. Chandrakasan, “Flexible Low Power CNN Accelerator for Edge Computing with Weight Tuning,” A-SSCC 2019. [link]
• Koppula S., J. Glass, A. P. Chandrakasan, “Energy-Efficient Speaker Identification with Low-Precision Networks,” ICASSP 2018. [link]
• Biswas A., A. P. Chandrakasan, “Conv-RAM: An Energy-Efficient SRAM with Embedded Convolution Computation for Low-Power CNN-Based Machine Learning Applications,” ISSCC 2018. [link]
• Tikekar M., V. Sze, A. P. Chandrakasan, “A fully-integrated energy-efficient H.265/HEVC decoder with eDRAM for wearable devices,” VLSIC 2017. [link]
• Price M., J. Glass, A. P. Chandrakasan, “A Scalable Speech Recognizer with Deep-Neural-Network Acoustic Models and Voice-Activated Power Gating,” ISSCC 2017. [link]
• Raina P., M. Tikekar, A. P. Chandrakasan, “An energy-scalable accelerator for blind image deblurring,” ESSCIRC 2016. [link]
• Biswas A., A. P. Chandrakasan, “A 0.36V 128Kb 6T SRAM with energy-efficient dynamic body-biasing and output data prediction in 28nm FDSOI,” ESSCIRC 2016. [link]
• Jeon, D., N. Ickes, P. Raina, H. C. Wang, A. P. Chandrakasan, “A 0.6V 8mW 3D vision processor for a navigation device for the visually impaired,” ISSCC 2016. [link]