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Energy-Efficient Circuits and Systems Group
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Hardware Security

The sheer number and diversity of IoT devices, along with their limited resources, makes IoT security a challenge quite different from securing traditional computing systems.

As a circuits and systems group, we have been working on the design of low-power cryptographic hardware accelerators, wireless authentication tags, and energy-efficient security protocols. Apart from the traditional approach, we are also exploring novel applications of security like secure analog-to-digital converters, secure neural networks accelerator, and attacks on sparse neural networks.
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Research Team

Maitreyi Ashok

Seoyoon Jang

Related Recent Publications

  • Maji S., U. Benerjee, S. H. Fuller, A. P. Chandrakasan, “A Threshold-Implementation-Based Neural-Network Accelerator Securing Model Parameters and Inputs Against Power Side-Channel Attacks,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2022. [link]
  • Maji S., U. Banerjee, S. H. Fuller, R. T. Yazicigil, A. P. Chandrakasan, “Securing Embedded Medical Devices using Dual-Factor Authentication,” IEEE International Symposium on Computer-Based Medical Systems (CBMS), Jun. 2021. [link]
  • Banerjee U., A. P. Chandrakasan, “A Low-Power Elliptic Curve Pairing Crypto-Processor for Secure Embedded Blockchain and Functional Encryption,” IEEE Custom Integrated Circuits Conference (CICC), Apr. 2021. [link]
  • Maji S., U. Banerjee, A. P. Chandrakasan, “Leaky Nets: Recovering Embedded Neural Network Models and Inputs through Simple Power and Timing Side-Channels – Attacks and Defenses,” IEEE Internet of Things Journal, Feb. 2021. [link]
  • Jeong T., A. P. Chandrakasan, H. S. Lee, “S2ADC: A 12-bit, 1.25MS/s Secure SAR ADC with Power Side-Channel Attack Resistance,” CICC 2020. [link]
  • Maji S., U. Banerjee, S. H. Fuller, M. R. Abdelhamid, P. M. Nadeau, R. T. Yazicigil, A. P. Chandrakasan, “A Low-Power Dual-Factor Authentication Unit for Secure Implantable Devices,” CICC 2020. [link]
  • Ibrahim M. I., M. I. W. Khan, C. S. Juvekar, W. Jung, R. T. Yazicigil, A. P. Chandrakasan, R. Han, “THzID: A 1.6mm2 Package-Less Cryptographic Identification Tag with Backscattering and Beam-Steering at 260GHz,” ISSCC 2020. [link]
  • Banerjee U., T. S. Ukyab, A. P. Chandrakasan, “Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols,” CHES 2019. [link]
  • Banerjee U., A. Pathak, A. P. Chandrakasan, “An Energy-Efficient Configurable Lattice Cryptography Processor for the Quantum-Secure Internet of Things,” ISSCC 2019. [link]
  • Juvekar C., V. Vaikuntanathan, A. P. Chandrakasan, “GAZELLE: A Low Latency Framework for Secure Neural Network Inference,” USENIX Security 2018. [link]
  • Yazicigil R. T., P. Nadeau, D. Richman, C. Juvekar, K. Vaidya, A. P. Chandrakasan, “Ultra-Fast Bit-Level Frequency-Hopping Transmitter for Securing Low-Power Wireless Devices,” RFIC 2018. [link]
  • Abdelhamid M. R., A. Paidimarri, A. P. Chandrakasan, “A −80dBm BLE-compliant, FSK wake-up receiver with system and within-bit dutycycling for scalable power and latency,” CICC 2018. [link]
  • Banerjee U., C. Juvekar, A. Wright, Arvind, A. P. Chandrakasan, “An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for End-to-End Security in IoT Applications,” ISSCC 2018. [link]
  • Banerjee U., C. Juvekar, S. H. Fuller, A. P. Chandrakasan, “eeDTLS: Energy-Efficient Datagram Transport Layer Security for the Internet of Things,” GLOBECOM 2017. [link]
  • Desai N., C. Juvekar, S. Chandak, A. P. Chandrakasan, “An Actively Detuned Wireless Power Receiver with Public Key Cryptographic Authentication and Dynamic Power Allocation,” ISSCC 2017. [link]
  • Juvekar, C. S., H. M. Lee, J. Kwong, A. P. Chandrakasan, “A Keccak-based wireless authentication tag with per-query key update and power-glitch attack countermeasures,” ISSCC 2016. [link]